中文AV岛国无码免费播放

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    74LS112/54LS112 pdf datasheet

    資料大?。?/em> 13

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    上傳日期: 2008-08-06

    上 傳 者: 發燒友他上傳的所有資料

    資料介紹

    標簽:74LS1(28)
    54LS112/DM54LS112A/DM74LS112A
    Dual NegaTIve-Edge-Triggered Master-Slave
    J-K Flip-Flops with Preset, Clear,
    and Complementary Outputs
    General DescripTIon
    This device contains two independent negaTIve-edge-triggered
    J-K flip-flops with complementary outputs. The J and
    K data is processed by the flip-flop on the falling edge of the
    clock pulse. The clock triggering occurs at a voltage level
    and is not directly related to the transiTIon time of the falling
    edge of the clock pulse. Data on the J and K inputs may be
    changed while the clock is high or low without affecting the
    outputs as long as the setup and hold times are not
    violated. A low logic level on the preset or clear inputs will
    set or reset the outputs regardless of the logic levels of the
    other inputs.
    Features
    Y Alternate Military/Aerospace device (54LS112) is available.
    Contact a National Semiconductor Sales Office/
    Distributor for specifications.

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    中文AV岛国无码免费播放

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